HP=HP, HW=HW
Background Plane Setting Full Image Horizontal Size Register
| HW | Background plane horizontall valid pixel width on the basis of pixel clock (PXCLK)Note: When serial RGB is selected as the output format for the output control block, add two to the horizontal enable signal width and set the resulting value to this field. 0 (HW): HW cycles. The valid range is 0x010 to 0x3F8. |
| HP | Background plane horizontal valid pixel start position on the basis of pixel clock (PXCLK). 0 (HP): HP cycle(pixel). The valid range is 0x006 to 0x3EE. |